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All Compact Discs deliver 44100 stereo samples per second, 16 bits per channel; no more, no less. Only the time capacity of the disc varies. Over the last 5 years this has increased from about 70 to 80 minutes. The CD standard has a large margin for the range of acceptable linear track velocity, from 1.2 to 1.4 metres per second, and the track pitch can be reduced from 1.6 to 1.4 micrometres. By using the lowest limit, the capacity is increased. Of course, the disc production quality must be higher, as the bump transition multiple on the tracks reduces from 0.324 micrometres down to 0.278 micrometres.

There are many ways of converting the discrete digital numbers into a continuous analog waveform. Because of technological limitations and fabrication costs of chips, some early players only converted the 14 most significant bits, ignoring the other two. A single Digital to Analog Converter (DAC) was shared by both channels, switching inputs and outputs between left and right every 11.3 microseconds. This resulted in a time delay between the channels, which could be allowed for by moving the loudspeaker cabinet of the delayed channel forward by 3.52 millimetres.

**Figure 1: Then**

Channel interaction effects in the converter can also occur. High-order active analog filters were also required to eliminate sampling artifacts; these introduced phase aberrations and comb-filter effects in the midrange frequencies and above, blurring the spatial information. Refer to Figure 1.

**Figure 2: Now**

Things have come a long way since then. Dual 16 bit DACs are now manditory. Digital filtering and over-sampling reduce the requirements for the removal of sampling artifacts in the audio stages. Simple second or third order filters need only be used, decreasing the number of analog components required, and those nasty effects. Refer to Figure 2. I will now slow down the pace and explain each part step by step.

Numerous designs exist for DACs, suited to different needs. Only two meet the high demands for digital audio. Dynamic Element Current Summing is preferred by Philips, and the Dual Integrator method is preferred by Sony.

**Figure 3: Current Summer**

The first method relies on a summer with a set of switched input currents in precise 2:1 ratios, controlled by the 16 digital input bits, see Figure 3. The problem here is that the sum of the 15 Least Significant Bit (LSB) currents must be matched to the Most Significant Bit (MSB) current to an accuracy of one part in 2 to the power of 16, or 65536 or 0.0015%; a tall order for seperate current sources.

**Figure 4: Current Summer with Dividers**

The circuit can be redrawn if current dividers are used instead of individual current sources, as in Figure 4, and the desired accuracy is achieved.

**Figure 5: Dynamic Current Splitting Element**

A current divider can be constructed using two loose tolerance resistors, two loose tolerance capacitors and two switches that are driven by a clock with a very precise 50% duty cycle. The average output currents are exactly half the input current. A circuit is in Figure 5. The big advantage of this design is that it requires no calibration, making it suitable for mass production.

**Figure 6: Integrator Converter**

The second method combines two integrator converters. This type uses a constant current charging a capacitor, producing a linear voltage rise over time. If the time period is determined by a binary counter that is counting up to the value of the digital input, the final output voltage of the capacitor will be the analog equivalent of the digital input. Schematic gurus may now peruse Figure 6. The counter clock must run at the sample rate times the number of possible digital sample values. For CD, this is 44100 x 65536 = 2890 MegaHertz!

**Figure 7: Dual Integrator Converter**

The practical solution is to use dual cascaded integrators with a precise current ratio of 256, as in Figure 7. This requires a counter clock of 44100 x 256 x 2 = 22 MHz, a realistic figure for LSI logic.

**Figure 8: A Conversion Example**

Both types of converters require a finite time to perform a conversion, and the analog output is valid only for a short time during each cycle. A sample-and-hold circuit (S/H) follows the converter, to maintain a constant output voltage until the next conversion is complete. This output voltage appears as a stair-case. Figure 8 shows a representation of the whole conversion process to this point, for a simple 3 bit system.

The subjects to be tackled next are over-sampling and filtering.

Figures 1 to 8 - Hand drawn by Glenn Baddeley, 1989;
Figures 3 to 7 based on figures in
J.R. Watkinson, *Compact Disc Players - 2*, **Electronics & Wireless World** magazine, November 1985, pp29-33

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Originally published in **MAC Audio News** No. 179, December 1989, pp 34-38.